Many of today's integrated circuits require signal delay circuits to provide proper timing of signals both internal and external to the integrated circuits. It is often desired that the delay time introduced by such a delay circuit, i.e., the time by which the delay circuit delays a signal, meet tight tolerance requirements. That is, it is often desired that the delay time lie within a narrow range to insure that an integrated circuit operates properly.
A problem with many existing delay circuits is that their delay times vary significantly as the power-supply voltage (for the integrated circuits containing the delay circuits) changes or shifts from a predetermined or desired voltage. Poor regulation of the desired power-supply voltage is one cause of such shifting.
Furthermore, because its delay time is sensitive to variations in the supply voltage, such a delay circuit prohibits an engineer from using an integrated circuit that incorporates the delay circuit in a system that uses a supply voltage that is different from the desired voltage. For example, popular supply voltages for electronic systems include 5.0V and 3.3V. If a delay circuit is designed to provide a predetermined delay with a 5.0V supply, the integrated circuit containing the delay circuit often cannot be used in a 3.3V system. Of course, one may design a version of the integrated circuit that includes a delay circuit for providing the desired delay with a 3.3V supply voltage. However, designing different versions of an integrated circuit that work with different supply voltages is often time consuming and prohibitively expensive.
FIG. 1 is a schematic diagram of a known delay circuit 10, which provides a delay time that changes as the supply voltage V.sub.DD changes. The delay circuit 10 includes two primary delay stages 12a and 12b, an intermediate stage 14, and an output stage 16, which are all serially coupled between an input terminal 17 and an output terminal 19.
In operation, when an input logic signal at the input terminal 17 transitions from a logic 1 to a logic 0, the circuit 10 introduces a falling-edge delay time Dft to the input logic signal composed of the sum of the delay times of the delay stages 12a and 12b. Specifically, the stage 12a introduces a falling-edge delay time Dfa to the input logic signal. As the level of the logic signal reaches and falls below the switching threshold, i.e., trip point, of the stage 12a, the transistors 20a and 20b turn off, i.e., become inactive, and the transistors 18a and 18b turn on, i.e., become active. The active transistors 18a and 18b allow a charge current to flow between V.sub.DD and the capacitor Ca. The falling-edge delay Dfa is the time it takes for the charge current to charge the capacitor Ca to a voltage that equals the trip point of the next stage 12b. Thus, the values of Ca and the charge current determine the falling-edge delay Dfa, which increases as Ca increases or the charge current decreases, and decreases as Ca decreases or the charge current increases.
When the logic signal generated by the stage 12a transitions from a logic 0 to a logic 1 (in response to the logic-1-to-logic-0 transition of the input signal), the stage 12b introduces a second falling-edge delay Dfb to the input logic signal. Although the stage 12a inverts the input logic signal so as to provide a rising edge to the stage 12b, the delay that the stage 12b introduces to the logic signal from the stage 12a is referenced to the input logic signal, and is thus referred to as a falling-edge delay. Specifically, as the voltage across the capacitor Ca charges to and above the trip point of the delay stage 12b, the transistors 18c and 18d turn off, and the transistors 20c and 20d turn on. The active transistors 20c and 20d allow a discharge current to flow between the capacitor Cb and ground. The falling-edge delay Dfb is the time it takes for the discharge current to discharge the capacitor Cb to a voltage that equals the trip point of the next stage 14. Thus, the values of Cb and the discharge current determine the falling-edge delay Dfb, which increases as Ca increases or the discharge current decreases, and decreases as Ca decreases or the discharge current increases.
The falling-edge delay introduced to the input logic signal by the intermediate stage 14 is typically much less than the falling-edge delays Dfa and Dfb, and thus is typically ignored. As the voltage across the capacitor Cb discharges to and below the trip point of the intermediate stage 14, the transistors 22a and 22b turn on, and the transistors 24a and 24b turn off. The active transistors 22a and 22b allow a charge current to flow between V.sub.DD and the parasitic capacitance Cp, which is typically much smaller than Ca or Cb. Thus, the voltage across Cp charges relatively quickly to the trip point of a conventional inverter 26, which provides the falling edge of an output logic signal the delay time Dft after the falling edge of the input logic signal. The delay of the inverter 26 is also typically much less than Dfa and Dfb, and thus is also typically ignored.
It is clear from the above description that the total delay time Dft of the circuit 10 is approximately equal to Dfa +Dfb. Therefore, by adjusting the falling-edge delays Dfa and Dfb of the stages 12a and 12b, respectively, one can set the total falling-edge delay Dft of the circuit 10 to a desired value.
Still referring to FIG. 1, when the input logic signal transitions from a logic 0 to a logic 1, the circuit 10 introduces a total rising-edge delay Drt to the input logic signal. Drt is approximately equal to Dra+Drb, where Dra is the rising-edge delay of the stage 12a, and Drb is the rising edge delay of the stage 12b. In a manner similar to that described above for the falling-edge delay, the transistors 20a and 20b allow a discharge current to flow between Ca and ground, the transistors 18c and 18d allow a charge current to flow between V.sub.DD and Cb, the transistors 24a and 24b allow a discharge current to flow between Cp and ground, and the inverter 26 provides the rising edge of the output logic signal the delay time Drt after the rising edge of the input logic signal.
Typically, the delay circuit 10 is designed to provide a predetermined delay time D at a predetermined voltage V.sub.DD for both Drt and Dft, i.e., D=Drt=Dft. However, if V.sub.DD varies or shifts to another voltage level, then Drt and Dft may become unequal to each other, and may both become unequal to D. Such shifts in Drt and Dft have many causes. For example, the logic 0 of the input logic signal typically is equal to approximately 0 volts, and the logic 1 is typically equal to approximately V.sub.DD. As V.sub.DD shifts, the logic 1 voltage level of the input logic signal shifts, as do the gate-to-source voltages applied to the transistors 18a-d and 20a-d. The shift in the gate-to-source voltages causes these transistors to provide different charge and discharge currents to the capacitors Ca, Cb, and Cp, respectively. As stated above, changes to the charge and discharge currents cause changes in Dra, Drb, Dfa, and Dfb, and thus cause changes in Drt and Dft. Furthermore, as V.sub.DD changes, so do the trip points of the stages 12a, 12b, 14, and 16. Thus, the combination of the changing gate-to-source voltages and the changing stage trip points often alters Drt and Dft of the circuit 10 significantly. Table 1 shows the delays Drt and Dft that one embodiment of the circuit 10 provides for V.sub.DD equal to 2.8 V, 3.3 V, and 4.0 V. This embodiment of the circuit 10 is designed to provide D=Drt=Dft=3 nanoseconds (ns) for V.sub.DD =3.3V.
TABLE 1 ______________________________________ V.sub.DD = 2.8 V V.sub.DD = 3.3 V V.sub.DD = 4.0 V (Drt/Dft) (Drt/Dft) ______________________________________ 3.45 nanoseconds (ns)/3.7 ns 3 ns/3 ns 2.23 ns/2.2 ns ______________________________________
As shown in Table 1, as V.sub.DD moves from 3.3 V, Drt and Dft become unequal to D as well as unequal to each other.